Using the register model: The register model has a set of variables for desired and mirror register values. The dotted lines indicate that you can generate register models for different methodologies: The figure below illustrates the flow to convert the RALF format into the register model using Synopsys Ralgen tool. You are perhaps familiar with the widely used Synopsys RALF format. Converting the specification into UVM register modelĬreating the register format specification: There are many register formats available to describe the designer’s register specification.Creating the register format specification.Here’s where you can find more information on our Verification IP.īefore I introduce the table, let us take a look at the process of creating the register model: After spending some time, I came up with a table which helped me to understand the behavior of register model APIs, and how best they can be called. I also felt that the terms used do not reflect the intent precisely. When I began using UVM RAL, I could not understand what the UVM base class library had to say about updating the values of desired value and mirror value registers.
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